A phase locked loop (PLL) circuit having high phase noise performance is suitably used as a spectrum analyzer or an oscillation circuit such as a signal generator (see, for example, Patent Document 1).
FIG. 4 shows a basic configuration of a PLL circuit of the related art. A PLL circuit 40 of the related art includes a reference signal generation unit 41 that generates a reference signal, a voltage controlled oscillator (VCO) 42 that controls the frequency of an output signal in accordance with the voltage of an input signal, a phase frequency detector (PFD) 43 that outputs a phase difference signal according to a phase difference between the output signal from the VCO 42 and the reference signal, and a loop filter 44 that allows passage of a low-frequency component of the phase difference signal to input the low-frequency component to the VCO 42.
The PLL circuit 40 includes a plurality of low-pass filters (LPFs) having different frequency ranges which are capable of reduce phase noise, as the loop filter 44 for optimizing the phase noise for each offset frequency. The term “offset frequency” as used herein refers to a frequency indicated using the center frequency of the output signal from the VCO 42 of the PLL circuit 40 as a reference (zero). The plurality of LPFs are configured such that only one LPF is selected by a switch 45.